Design and test bench:
//***** design under test******// design top module
module mux4(
//input interface
input [3:0]i,
input[1:0]s,
input [1:0]e,
output o
);
// intermediate signals
wire x,y,e0,e1,e3,s1n;
// design mux with structural style modeling
not n1 (s1n,s[1]);
mux2 m20(i[1:0],s[0],s1n,x); // connection with MUX2 port by position i[1:0],s,e,o
mux2 m21(i[3:2],s[0],s[1],y); // connection with MUX2 port by position i[1:0],s,e,o
and a1 (e0,x,e[0],e[1]);
and a2 (e1,y,e[0],e[1]);
and a3 (e3,e[0],e[1]);
mux2 m22({e1,e0},s[1],e3,o); // connection with MUX2 port by position i[1:0],s,e,o
endmodule
// desing component
module mux2(
input [1:0]i,
input s,
input e,
output o);
// intermediate signals
wire x,y,ns;
// design the dataflow
assign ns = ~s;
assign x= ns & i[0] & e;
assign y= s & i[1] & e;
assign o = x|y;
endmodule
//***** test bench module******
// creating test environment for DUT
module tb_mux4X1( );
reg [3:0]i;
reg [1:0]s;
reg [1:0]e;
wire o;
// taking instance of the mux4X1
mux4 m41(i[3:0],s[1:0],e[1:0],o); // connection with MUX2 port by position i[3:0],s[1:0],e[1:0],o
initial
begin
$dumpfile("mux4X1_str.vcd");
$dumpvars(-1,m41);
end
always
begin
// note that we take enble signals e[1:0] will be always 1
// only one input will activate at a time
i=4'h1;e=2'b11;s=2'b00;#10; // s=0 and i=1 line 0 high
i=4'h2;e=2'b11;s=2'b01;#10; // s=1 and i=2 iine 1 high
i=4'h4;e=2'b11;s=2'b10;#10; // s=2 and i=4 line 2 high
i=4'h8;e=2'b11;s=2'b11;#10; // s=3 and i=8 line 3 high
// random selection and activation of input
i=4'h2;e=2'b11;s=2'b01;#10;
i=4'h3;e=2'b11;s=2'b10;#10;
i=4'h7;e=2'b11;s=2'b11;#10;
i=4'h9;e=2'b11;s=2'b10;#10;
i=4'h4;e=2'b11;s=2'b01;#10;
i=4'hE;e=2'b11;s=2'b00;#10;
//finish
$finish;
end
endmodule
Waveform:
