//To refer basic half adder and full adder design click here
// To refer parallel adder design click here
// this is the behavioral implementation of the 16bit parallel adder.
// this adder will work similar to the parallel adder with data flow modeling.
// ************Design under test (DUT)********************
module adder16gen(
// defining input output ports
input [N:0] a,
input [N:0] b,
input cin,
output [N:0] s,
output cout);
parameter N=15; // generic parameter
wire [N+1:0]t; // for temporary storage
assign t=a + b + cin; // addition of input data
assign s[N:0] = t [N:0]; // assign the temporary to output
assign cout = t[N+1]; // Answer's MSB will assign to cout
endmodule
//************** test bench module **********************
module tb();
parameter N=15; // test bench generic paramenter
//defining regs and wires to connect with DUT terminals
reg [N:0] a;
reg [N:0] b;
reg cin;
wire [N:0] s;
wire cout;
// take instance of the DUT in test bench
adder16gen i(a,b,cin,s,cout);
// defining the paramenters for simulation
initial begin
$dumpfile("adder16.vcd");
$dumpvars(-1,i);
end
// defining initial value of the input data
initial begin
a = 4'b0000; b=4'b0000;cin=1'b0;
end
// generate value for the test the design
always begin
#10;
// random value assigning to the ports
a=$random;b=$random;cin=$random;
#10;
a=$random;b=$random;cin=$random;
#10;
a=$random;b=$random;cin=$random;
#10;
a=$random;b=$random;cin=$random;
#10;
a=$random;b=$random;cin=$random;
#10;
a=$random;b=$random;cin=$random;
//finish the test code with $finish command
$finish;
end
endmodule
Test commands: to get more insight for testing design click here
Result:
