Design the half adder in verilog on iverilog simulator with GTKwave analyser

Half adder :

 Design file:

module half_adder(
input a,b,
output s,c);

assign s = a^b;
assign c = a&b;

endmodule

Test bench:

module half_adder_tb();

reg a,b;
wire s,c;

half_adder ha_1( .a(a), .b(b), .s(s),.c(c));

initial begin
    $dumpfile("half_adder.vcd");
    $dumpvars(-1,ha_1);
end

initial begin
    
    a=1'b0 ; b=1'b0;
    #10
    a=1'b0 ; b=1'b1;
    #10
    a=1'b1 ; b=1'b0;
    #10
    a=1'b1 ; b=1'b1;
    #10;   
end

endmodule

Executing code :

PART1: For Windows System command line

iverilog half_adder_tb.v half_adder.v

iverilog -o half_adder half_adder_tb.v half_adder.v

iverilog -o half_adder.vvp -tvvp half_adder_tb.v half_adder.v

vvp half_adder

gtkwave half_adder.vcd

Waveform:

 

PART2: Write Makefile on ubunt18.04

TARGET = half_adder

CC = iverilog

$(TARGET) : $(TARGET).v

$(CC) $(TARGET)_tb.v $(TARGET).v

$(CC) -o $(TARGET) $(TARGET)_tb.v $(TARGET).v

$(CC) -o $(TARGET).vvp -tvvp $(TARGET)_tb.v $(TARGET).v

vvp $(TARGET)

run: 

gtkwave $(TARGET).vcd

clean:

rm $(TARGET) $(TARGET).vvp $(TARGET).vcd 

To test the code from ubuntu terminal

make 

make run

make clean

To refer the full adder code click here

To refer the parallel adder code with structural style modelling click here

To refer the parallel adder code with behavioral style modelling click here