Design the full adder in verilog using icarus verilog and gtk wave

Full adder:

Design file:

module full_adder(
input a,b,cin,
output s,c);

assign s = a ^ b ^ cin;
assign c = (a & b)|(b & cin)|(cin & a);
endmodule

Test bench:

module full_adder_tb();

reg a,b,cin;
wire s,c;

full_adder fa_1( .a(a), .b(b), .cin(cin), .s(s), .c(c));

initial begin
    $dumpfile("full_adder.vcd");
    $dumpvars(-1,fa_1);
end

initial begin
    
    a=1'b0 ; b=1'b0; cin=1'b0 ;
    #10
    a=1'b0 ; b=1'b0; cin=1'b1 ;
    #10
    a=1'b0 ; b=1'b1; cin=1'b0 ;
    #10
    a=1'b0 ; b=1'b1; cin=1'b1;
    #10;   
    a=1'b1 ; b=1'b0; cin=1'b0;
    #10
    a=1'b1 ; b=1'b0; cin=1'b1;
    #10
    a=1'b1 ; b=1'b1; cin=1'b0;
    #10
    a=1'b1 ; b=1'b1; cin=1'b1;
    #10;
    
end

endmodule

Waveform:

l

To refer code of half adder click here

To refer basic steps of Icarus verilog and GTKWave click here