Design parallel adder using verilog and simulate on iverilog and observe the waveform through GTKwave

Basic module of full adder

module full_adder(
input a,b,cin,
output s,c);

assign s = a ^ b ^ cin;
assign c = (a & b)|(b & cin)|(cin & a);
endmodule
 

Design file

module adder16(input [15:0]a,
input [15:0]b,
input cin,
output [15:0]s,
output cout);

wire [14:0]co;

full_adder i1(a[0],b[0],cin,s[0],co[0]);
full_adder i2(a[1],b[1],co[0],s[1],co[1]);
full_adder i3(a[2],b[2],co[1],s[2],co[2]);
full_adder i4(a[3],b[3],co[2],s[3],co[3]);
full_adder i5(a[4],b[4],co[3],s[4],co[4]);
full_adder i6(a[5],b[5],co[4],s[5],co[5]);
full_adder i7(a[6],b[6],co[5],s[6],co[6]);
full_adder i8(a[7],b[7],co[6],s[7],co[7]);
full_adder i9(a[8],b[8],co[7],s[8],co[8]);
full_adder i10(a[9],b[9],co[8],s[9],co[9]);
full_adder i11(a[10],b[10],co[9],s[10],co[10]);
full_adder i12(a[11],b[11],co[10],s[11],co[11]);
full_adder i13(a[12],b[12],co[11],s[12],co[12]);
full_adder i14(a[13],b[13],co[12],s[13],co[13]);
full_adder i15(a[14],b[14],co[13],s[14],co[14]);
full_adder i16(a[15],b[15],co[14],s[15],cout);

endmodule

// test bench is included with the design file

 
module adder16_tb();
reg [15:0]a;
reg [15:0]b;
reg cin;
wire [15:0]s;
wire cout;

adder16 i(a[15:0],b[15:0],cin,s[15:0],cout);

initial begin
    $dumpfile("test.vcd");
    $dumpvars(-1,i);
end

initial begin
    a=16'h2345; b=16'h3489 ; cin = 1'b1 ; #100
    a=16'hA375; b=16'hB48C ; cin = 1'b0 ; #100
    a=16'hAB09; b=16'h0348 ; cin = 1'b1 ; #100
    a=16'h1098; b=16'h3489 ; cin = 1'b0 ; #100
    a=16'h1098; b=16'h3489 ; cin = 1'b1 ; #100;
end
endmodule

Steps to execute the code

Step1: iverilog adder16.v full_adder.v

Step2: iverilog -o adder_16 adder16.v full_adder.v

Step3: iverilog -o adder_16.vvp -tvvp adder16.v full_adder.v

Step4: vvp adder_16

Step5: gtkwave test.vcd

Waveform: